1. Field of the Invention
The present invention relates to a shear testing apparatus, and in particular to a shear testing apparatus with a removable platform to accommodate different sized silicon substrates.
2. Description of the Related Art
Currently, in order to remain competitive in the IC industry, IC process engineers continuously strive to reduce the overall size and corresponding cost of IC devices. As a result of this trend toward smaller overall size, sizes of individual features of the IC device and package have decreased and circuit density has correspondingly increased. Many IC engineers pursue ways to significantly increase the feature density to take full advantage of significant decreases in feature size and thereby reduce the overall size of the IC package. Additionally, to take full advantage of significantly increased feature density, IC engineers attempt to increase the I/O pin density of IC packages. With these goals in mind, IC chip engineers have developed a wide variety of package designs to maximize I/O pin density and reduce overall package size.
One example of a package design that has a relatively high I/O density is the flip chip type package. The typical flip chip package includes an array of pads to provide interconnections between the IC devices within the die and other electrical components or IC devices external to the die. An array configuration allows the engineer to utilize the package area for I/O pad placement, as opposed to other package designs, such as surface mount packages, which typically provide I/O pins only around the package periphery.
Another example of a package design with a relatively high I/O density is the chip scale package (CSP). The typical CSP has overall package dimensions substantially equal to that of the active silicon device or die that is enclosed within the package. One such type of CSP is manufactured in wafer form and is referred to as a wafer level CSP or WLCSP. A surface mount die is a WLCSP in which I/O contacts are in bump form and located on the active side of the die.
FIG. 1A shows a die 10 of a conventional flip chip typically including a plurality of fabricated IC device structures (not shown). These IC device structures may include, for example, transistors and interconnect layers. The top surface 11 of the die has a plurality of under bump pads (not shown) formed thereon. Contact bumps 12 are formed on the under bump pads of the topmost surface 11 to provide both mechanical and electrical connections. The bottom surface of the wafer is conventionally left bare, or exposed. That is, the bottom surface is typically bare silicon.
FIG. 1B shows an enlarged cross section of a contact bump of a WLCSP die. In FIG. 1B, the conductive pad 13 is patterned over the active top surface of the die 10 and electrically connected to conventionally fabricated IC device structures (not shown). A passivation layer 14 is formed on the WLCSP die 10, covering the top surface thereof except for the conductive pad 13, to protect the IC devices therein. The under bump pad 15 is formed over portions of the passivation layer 14 and the conductive pad 13. The contact bump 12 is then grown onto the under bump pad 15.
In the conventional semiconductor process, the contact bump 12 is applied to the silicon substrate by re-flowing processes to form a semi-circular bump. It is necessary to test the mechanical strength of the intermetallic bond between the gold or solder deposit and the substrate in order to determine that the bonding method is adequate, and that the bond strength is sufficient. Difficulties arise because of the very small dimensions of the components, the precision with which the testing device must be positioned, and the very small forces and deflections which are to be measured.
In FIG. 2, the conventional test method applies a precision, thin and flat shear tool, or a probe 22, to test the adhesion between deposits and the substrate, before the dies are separated from the wafer 1 in a dicing or singulation procedure. First, the wafer 1 is fixed on a stage 21 of the test apparatus. The probe 22 is moved by some mechanical means to a start point. In order to avoid friction caused by the tool rubbing on the surface of the substrate, it is necessary for the probe 22 to be just above the substrate surface. The height of the probe 22 must be closely controlled to provide accurate force measurement, typically within +−1 μm. The probe 22 typically makes an initial point contact with the contact bump 12 on the wafer 1. The probe 22 is moved along the direction of arrow (a) and applied to the side of the contact bump 12 and moved in the direction of arrow (a) to test the mechanical strength of the bond between the contact bump 12 and the substrate. Eventually, the contact bump 12 will break, and the magnitude of the force to shear the contact bump 12 from the substrate is determined by conventional strain gauge techniques.
Furthermore, in U.S. Pat. No. 6,341,530, Sykes teaches a modified probe described for testing the force to shear a deposit of solder or gold from a substrate. These deposits have a diameter in the range 50–100 μm and serve as bonds for electrical conductors. A shear tool has a semi-cylindrical cavity which closely approximates the mean diameter of a range of substrates. This tool is adapted to re-shape substrates for a better fit. Re-shaping occurs over 30% or less of the circumference of a deposit, and to a depth of 10% or less of the diameter of the substrate.
The conventional shear test is carried out on a whole wafer. As a result, the stage and the means of moving the conventional shear test apparatus must be re-designed for each different wafer size, such as 6″, 8″ and 12″ wafers, and semiconductor factories must prepare different shear test apparatuses for different sizes of wafers, thus increasing the cost of the apparatus. Hence, there is a need for a better shear testing method and apparatus which overcomes the aforementioned problems.